Programmable logic devices (PLDs) are general-purpose circuits that can be programmed by an end user to perform one or more selected functions. Complex PLDs (may also be referred to herein as programmable logic arrays) typically include a number of programmable logic elements and some programmable routing resources. Programmable logic elements have many forms and many names, such as Configurable Logic Blocks (CLBs), logic blocks, logic array blocks, logic cell arrays, macrocells, logic cells, and functional blocks. Programmable routing resources also have many forms and many names.
A field-programmable gate array (FPGA) is a popular type of PLD. FPGAs generally include an array of identical CLB tiles that are programmable both in function and connection to other CLBs. Some PLDs have been proposed that include fixed design memory blocks, such as Random Access Memory (RAM), and Read Only Memory (ROM) that can interface to the CLBs. Still other PLDs have been proposed that include fixed design digital signal processors and general processors that can interface to the CLBs.
However, many of the signal processors that are custom designed may have significant bottlenecks when having to interface with CLBs. Furthermore, some of the proposed signal processors are designed much like a general purpose processor with microcode to make it very flexible. However, this flexibility, while it may allow many possible operations, may also influence overall performance.
There is a need for an improved signal processor configured for flexibility to adapt for different applications and data characteristics yet structured enough to enhance performance for target applications. Furthermore, there is a need for an improved signal processor that can be incorporated in a programmable logic array.